Referring to FIG. 1A, a known, discrete high electron mobility transistor (HEMT) may include drain pad 10, source pad 12, and gate pad 14. Drain pad 10 is electrically connected to a plurality of drain runners 16, and source pad 12 is electrically connected to a plurality of source runners 18. Usually, drain pad 10 and source pad 12, and runners 16, 18 are arranged parallel to one another. In addition, in one conventional arrangement, drain runners 16 and source runners 18 are alternated in order to distribute current evenly through drain pad 10 and source pad 12. In a device according to FIG 1A, the area between each two opposing runners 16, 18 is an active area.
Referring next to FIG. 1B, a portion A of an active area of the device of FIG. 1A is enlarged to illustrate a plurality of drain fingers 20 that are electrically connected and extend away from each drain pad 10, and a plurality of source fingers 22 that are electrically connected to and extend away from each source pad 12. It should be noted that drain fingers 20 and source fingers 22 alternate along drain pad 16 and source pad 18, whereby an interdigitated configuration is attained. Gate electrode 24 meanders through the space between drain pad 16, drain fingers 20, source pad 18, and source fingers 22, and, although not shown, is connected to a gate runner which electrically connects gate electrode 24 to gate pad 14.
Referring next to FIG. 1C, a typical HEMT includes substrate 25, which may be formed from GaN, Si, SiC, or Sapphire, first semiconductor body 26 formed from one III-nitride semiconductor such as GaN and disposed over substrate 25, and a second semiconductor body 28 formed of another III-nitride semiconductor of a different band gap such as AlGaN disposed over first semiconductor body 26. First semiconductor body 26 and second semiconductor body 28 form heterojunction 30, which due to piezoelectric polarization forms a two dimensional electronic gas (2DEG) at or near heterojunction 30. The 2DEG so formed is highly conductive and serves as a channel for conducting current between a source finger 20 and a drain finger 22. It should be noted that in a typical device source fingers 22 and drain fingers 20 are connected to second semiconductor body 28 by a highly conductive ohmic contact layer 32.
In the device shown by FIG. 1C, gate electrode 24 is insulated form second semiconductor body 28 by gate insulation layer 34. In another variation, gate electrode 24 can make a schottky contact with second semiconductor body 28, as seen, for example, in FIG. 1D.
The devices illustrated by FIG. 1C and FIG. 1D are depletion mode devices, meaning that the device is nominally on and the activation of gate electrode 24 in each device by application of an appropriate voltage interrupts the 2DEG to turn the device off. Enhancement mode HEMTs are shown in U.S. Provisional Application Ser. No. 60/544,626, filed Feb. 12, 2004, the disclosure of which is incorporated herein by reference and U.S. patent application Ser. No. 11/056,062, entitled III-Nitride Bidirectional Switch, filed in the name of Daniel M. Kinzer and Robert Beach concurrently with the present application, the disclosure of which is incorporated by reference. Bidirectional devices can include one gate electrode, or two gate electrodes. FIG. 1E illustrates a bidirectional discrete device which includes two gate electrodes.
The prior art devices described with reference to FIGS. 1A-1E are discrete devices, meaning that each of these devices occupies a single, discrete semiconductor die. Due to the high breakdown voltage and current carrying capabilities III-nitride power devices occupy only a small area on a die. Thus, III-nitride-based semiconductor power devices are very small compared to silicon-based devices.
As with other devices, III-nitride semiconductor power devices need to be packaged so that they may be used in an electronic application, such as a power supply application, or motor control application. In a semiconductor package containing a III-nitride-based power semiconductor device, the packaging elements are thought to contribute the most to the overall size of the package due to the small size of the III-nitride power devices. Because many power applications require more than one power semiconductor device, it is expected that packaging, not the die, will contribute the most to the amount of space that is occupied by III-nitride-based power semiconductor packages.